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Re: [Kitchen] WVGA Touch Pro 2 Collaboration
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Sprint Evo LTE/3D, Iphone 32gb 4s
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Re: [Kitchen] WVGA Touch Pro 2 Collaboration
Have done, has not happened since but one user of my rom is reporting lockups...although he said his IE did not work at all and min is fine... said to him sounded like a bad lash too...
Well thanks for the feedback on nuespinlock http://www.nuerom.com/BlogEngine/pos...ckPatcher.aspx |
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Re: [Kitchen] WVGA Touch Pro 2 Collaboration
nueSpinLockPatcher is a tool to patch out the SWP containing procedures in HTC code – inside both drivers and the kernel. Its a tool designed for ROM cooks and developers – see the download page for links and information.
What does this mean? What are SWP? What are the advantages to being spinlocked. Help |
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Re: [Kitchen] WVGA Touch Pro 2 Collaboration
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hthomas hope this clears everything up for you! I think it has something to do with Sub Atomic Particles! SWP instruction The ARM SWP instruction is used to perform an atomic read-modify-write operation. It is commonly used with semaphores to guarantee that another process cannot modify a semaphore when it is being read by the current process. If the ARM966E-S performs a SWP operation to an AHB address location, the access is always performed as unbuffered to ensure that the core is stalled until the write has occurred on the AHB. The BIU asserts the HLOCK output to prevent the AHB arbiter from granting a different master, thus ensuring that the read-modify-write is atomic.
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"patching the smem.dll SWP instruction, and replaces branches to INTERRUPTS_ON and INTERRUPTS_OFF branches with the ARMv6 CPSID/CPSIE instruction, reducing the 5 instruction call to one instruction... For reference, I see no significant difference yet in synthetic benchmarks and 2% performance increase in CorePlayer FLV task. Actual performance gains you see will vary from device to device, but intuition tells me that latencies will decrease, which might not be measured by synthetic benchmarks." How does a SWP operation on a CPU translate in to bus activity? A SWP operation will result in a locked sequence of a read transaction followed by a write transaction to the same address. An interesting case to note is that if an error is received on the read operation the processor must perform another AXI transaction in order to complete the locked sequence and unlock the interconnect for other masters to use. In most cases it is likely that the locked sequence will be completed with a write transaction which has no write strobes asserted.
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Kitchen:Calkulin's VK for WVGA (Updated with Touch Pro 2 Collaboration)
ROM:Custom6.5.x(ScubaGear) My Files: Mediafire Folder When it's deserved, click Last edited by sc00b4s7eve; 08-04-2010 at 01:10 PM. Reason: corrected my info... I was way off |
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Other than the 2% increse in CorePlayer, will I notice any difference after spinlocking my OEMdrivers and oemxipkernel? What is meant by latencies will decrease? |
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