Quote:
Originally Posted by lionedas
hthomas hope this clears everything up for you!
I think it has something to do with Sub Atomic Particles! 
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Quote:
Originally Posted by sc00b4s7eve
nueSpinLockPatcher-1.1 updates and changelog (post date 5-22-09)
"patching the smem.dll SWP instruction, and replaces branches to INTERRUPTS_ON and INTERRUPTS_OFF branches with the ARMv6 CPSID/CPSIE instruction, reducing the 5 instruction call to one instruction...
For reference, I see no significant difference yet in synthetic benchmarks and 2% performance increase in CorePlayer FLV task. Actual performance gains you see will vary from device to device, but intuition tells me that latencies will decrease, which might not be measured by synthetic benchmarks."
How does a SWP operation on a CPU translate in to bus activity?
A SWP operation will result in a locked sequence of a read transaction followed by a write transaction to the same address. Actual performance gains you see will vary from device to device, but intuition tells me that latencies will decrease, which might not be measured by synthetic benchmarks."
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Other than the 2% increse in CorePlayer, will I notice any difference after spinlocking my OEMdrivers and oemxipkernel?
What is meant by latencies will decrease?